Register File First we are developing the 2 to 4 decoder module dec2x4 (out1, enable, select) input enable input select output out1 reg out1 always select) begin if (enable) begin case(select) 2'b00 out1 4'b0001 - 2'b01 : out1 4'b0010 2'b10 out1 4'b0100 2'b11 out1 4'b1000 endcase end else begin outi 4'b0000 end end endmodule The module for D flip flop is below module DFF (Q, clk, D) input clk input D output reg Q always (posedge clk) begin Q<= D end endmodule /We are now developing the 4 bit register to store the data based on load input and will give the output only on output enable (out_en) module Nibble_reg (data_out, clk, data_in, load, out_en) input clk input data_in input load input out_en output data_out wire data_i, data_o /instantiate D flip flops here DFF dff_O (.clk(clk). Create a Testbench in Verilog to test this out
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